Verification Series Part 4: UVM Projects
Writing Verilog test benches is always fun after completing RTL design. You can assure clients that the design will be bug-free in tested scenarios. As system complexity grows day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability, which help verification engineers quickly locate hidden bugs. System Verilog lags behind the structured approach, whereas UVM works hard to form a general skeleton. The addition of the configuration database shifts the way we used to work with the verification language in the past. Within a few years, verification engineers recognized the capabilities of UVM and adopted it as a de facto standard for RTL design verification. The UVM will have a long run in the verification domain; hence, learning about the UVM will help VLSI aspirants pursue a career in this domain.
This is a Lab-based course designed such that anyone with the fundamentals of UVM could understand how verification engineers use UVM to perform verification of commonly used RTLs and sub-blocks in FPGA. The course covers verification of the combinational circuit like combinational adder, Sequential circuit like Data flip-flop, communication interfaces like a clock generator, UART, SPI, and I2C, and Bus protocols like APB, AXI, and demonstration of few useful UVM concepts like a virtual sequencer, TLM analysis FIFO, and a sequence library.
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